1. Field of the Invention
The present invention is generally in the field of hardware-software coverification and in particular in the field of cycle and phase accurate hardware-software coverification.
2. Background Art
Prior to the advent of hardware-software coverification methods, verification of hardware-software systems was limited to running the software on a physical prototype of the hardware. The main drawbacks with that approach were that errors caught in the hardware prototype were typically very costly to fix, and often resulted in expensive hardware redesigns and significant delays in time-to-market.
In order to overcome the drawbacks of the traditional approach of performing system verification by running the software on a physical hardware prototype, tools and methods for hardware-software coverification were devised. In order to perform hardware-software coverification, the hardware is typically modeled using a Hardware Description Language (xe2x80x9cHDLxe2x80x9d) such as Verilog(copyright). Using an abstract HDL based hardware model, hardware-software coverification can be performed without the need for a physical hardware prototype. However, with the growing complexity of systems comprising a mix of micro controllers, digital signal processors (xe2x80x9cDSPsxe2x80x9d), RAMs, ROMs, dedicated logic, and various interconnect components, the coverification of the hardware and software designs has become a critical bottleneck in the system design process.
One problem with a thorough hardware-software coverification is the long time that is required to accurately verify any significant amount of software and hardware. Moving to higher levels of hardware abstraction and ignoring some level of detail has increased the speed of hardware-software coverification. In the late 1980""s gate-level simulators typically offered performance of about 2-10 instructions per second (xe2x80x9cIPSxe2x80x9d). In the early 1990""s Register Transfer Level (xe2x80x9cRTLxe2x80x9d) simulators improved performance to around 50 IPS. Even more recent hardware models in an HDL environment permit verification of merely 100 IPS. However, with some systems requiring hundreds of thousands of lines of code and millions of instructions to be run just to verify any significant portion of the system, the average system design simulations take hours or days to run, making it very difficult to quickly locate design errors or to test out design changes.
Increasing speed of hardware-software coverification requires more abstract hardware models. On the other hand, higher levels of hardware abstraction reduces the accuracy of the hardware-software coverification. In order to maintain accuracy of the hardware-software coverification, the hardware portion of the system should be modeled such that changes in input and output signals in the hardware (also referred to as xe2x80x9chardware eventsxe2x80x9d in the present application) are properly and reasonably timely reflected in the model.
For example, it is preferable that a change in an input or output signal in the hardware is detected, analyzed and reflected in the state of the system, and that the required system output is computed, all by the end of the clock cycle or the clock phase in which the change in the signal occurred. However, the present hardware-software coverification models are not able to account for and reflect changes in input and output hardware signals by the end of the clock cycle or clock phase in which a change occurs without significantly decreasing the speed of the hardware-software coverification.
In a paper entitled xe2x80x9cCycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-verification,xe2x80x9d authored by Lisa Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schlager, Bassam Tabbara, and Vojin Zivojnovic, and published in the Proceedings of 36th Design Automation Conference on June 21-25, 1999, New Orleans, LA, at pages 964-69, integration of xe2x80x9ccycle accuratexe2x80x9d and xe2x80x9cphase accuratexe2x80x9d instruction set architecture (xe2x80x9cISAxe2x80x9d) models of DSPs with other hardware and software components has been discussed. However, the paper does not disclose a hardware-software coverification model which detects, analyzes and reflects the state of the system, and computes the required system output, all by the end of the clock cycle or the clock phase without a significant decrease in the speed of the hardware-software coverification.
As apparent from the above discussion, there is need in the art for a hardware-software coverification model that is xe2x80x9ccycle accuratexe2x80x9d or xe2x80x9cphase accuratexe2x80x9d while substantially maintaining a high speed for performing a hardware-software coverification of the system.
The present invention is directed to and discloses a unique cycle and phase accurate hardware-software coverification. According to the invention, xe2x80x9ccycle accuratexe2x80x9d or xe2x80x9cphase accuratexe2x80x9d hardware-software coverification is performed while substantially maintaining a high speed for performing the coverification.
The invention comprises dividing system activities into a xe2x80x9cpre-computexe2x80x9d and a xe2x80x9cpost-computexe2x80x9d category. Those activities which fall in the pre-compute category are evaluated to ensure that updates to the state of the system are performed on a clock edge immediately following a change in system inputs affecting the state of the system. The state of the system is then updated on the same clock edge at which the pre-compute operation was performed. Those activities which fall in the post-compute category are then evaluated at the same clock edge on which the state of the system was updated. As a result of the post-compute operation, system outputs are timely generated while taking into account the change in the state of the system.
The division of system activities into those requiring pre-compute and those requiring post-compute substantially maintains a relatively high speed of hardware-software coverification. Also, the invention""s principles apply to a hardware-software coverification model where system inputs are evaluated and system outputs are generated at every clock rising edge (or at every clock falling edge depending on the convention used), i.e. a xe2x80x9ccycle accuratexe2x80x9d model, as well as to a coverification model where system inputs are evaluated and system outputs are generated at every clock rising edge and also at every clock falling edge, i.e. a xe2x80x9cphase accuratexe2x80x9d model.
The invention""s method of pre-compute, update, and post-compute, results in a timely evaluation of the status of those system inputs that affect the state of the system, a timely updating of the state of the system, and a timely generation of system outputs which depend on the updated state of the system.